Many digital circuit applications require communications between separate circuits implemented on different integrated circuit chips. Digital signals are communicated from one chip to another through a suitable transmission line or path. As used herein, "digital signals" refers to signals which reside at one of two signal voltage levels, a "low" voltage level representing one data state and a "high" voltage level representing the opposite data state. For example, a "low" voltage level signal may represent a "0" while a "high" voltage level signal may represent a "1". Often times a system may require that multiple signals be transmitted from one chip to another in the system. In these cases in which multiple signals must be communicated, the multiple signals may be communicated on different transmission lines or time division multiplexed on a single transmission line. In time division multiplexing, the multiple signals are simply transmitted at different times on the single transmission line.
Although time division multiplexing allows multiple signals to be transmitted over a single transmission line, it requires additional complex circuitry. In order to avoid the circuit complexity occasioned by time division multiplexing, system designs have often settled for using separate transmission lines in order to support simultaneous data communications in a single direction. However, multiple transmission lines also add complexity due to the added drivers, receivers, chip pins, and signal pads which the multiple transmission lines require. It is therefore also desirable to reduce the number of transmission lines between integrated circuit chips thereby reducing the corresponding connection, transmission, and reception circuitry.
U.S. patent application Ser. No. 08/387,518 is directed to a circuit for allowing simultaneous unidirectional data communications through a single transmission line. According the system disclosed in that application, two digital data signals are encoded into a single encoded signal which represents both original digital signals. The encoded signal is transmitted through a single transmission line to a second circuit which decodes the encoded signal back into the first and second digital data signals for use by the circuit on the receiving integrated circuit chip.
All transmission lines exhibit a parasitic resistance to the transmitted signals. For relatively short transmission lines this parasitic resistance is negligible and does not affect the transmitted signals. However, as the length of the transmission line increases the parasitic resistance may increase to the point at which the transmitted signal degrades sufficiently to cause an error in reading the transmitted data. The simultaneous signal transmission arrangement disclosed in patent application Ser. No. 08/387,518 is particularly susceptible to errors caused by signal degradation due to parasitic resistance in transmission lines. Since the encoded signal described in this patent application resides at one of four voltage levels between a supply voltage and ground, relatively little signal degradation may result in an error when decoding the encoded signal back to the desired data signals.